Instruction pipelining involves splitting a processing device (or processor) into a series of stages called a pipeline. The pipeline processes a stream of instructions such that the stages may operate on portions of different instructions concurrently. For example, an execution stage that follows a decode stage may execute a first instruction that has been decoded by the decode stage, while the decode stage simultaneously decodes a second instruction. Due to the simultaneous nature of operation of the pipeline stages, processor resources are thus used efficiently.
A conflict or data hazard occurs in the pipeline when there exists a dependency between instructions that coexist in the pipeline. For example, an instruction stream may include a subtraction instruction followed by a multiply instruction. The subtraction instruction subtracts the contents of a general purpose register (GPR) R1 from the contents of another GPR R2 and places the result in a third GPR R3. The subsequent multiply instruction multiplies the contents of the GPR R3 by itself and places the result in a fourth GPR R4. A data hazard exists because the multiply instruction may attempt to operate on the contents of the GPR R3 before the subtraction instruction has finished storing its result in the GPR R3. If the multiply instruction reads the contents of the GPR R3 before the subtraction result is stored in the GPR R3, the result of the multiply instruction will be incorrect.
A conventional method for avoiding data hazards that involve GPRs is for the processor to inspect each instruction as it arrives in the instruction stream. When an instruction arrives that may cause a data hazard, the processor drains the pipeline before advancing that instruction through the pipeline. Draining the pipeline typically involves waiting for all instructions existing in the pipeline to finish.
Another conventional method for avoiding data hazards that involve GPRs is to detect such hazards at compilation time. In particular, when a compiler compiles an application (one or more programs), the compiler generates instructions in such a way that they do not include data hazards.
In addition to GPRs, some processors have special registers for controlling, and for providing status relating to, the operation of the processor hardware. These special registers are called internal processor registers (IPRs).